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Espressif Systems /ESP32-S2 /SPI0 /LCD_CTRL2

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Interpret as LCD_CTRL2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0LCD_VSYNC_WIDTH 0 (VSYNC_IDLE_POL)VSYNC_IDLE_POL 0LCD_HSYNC_WIDTH 0 (HSYNC_IDLE_POL)HSYNC_IDLE_POL 0LCD_HSYNC_POSITION

Description

LCD frame control2 register

Fields

LCD_VSYNC_WIDTH

It is the position of spi_vsync active pulse in a line. Can be configured in CONF state.
VSYNC_IDLE_POL

It is the idle value of spi_vsync. Can be configured in CONF state.
LCD_HSYNC_WIDTH

It is the position of spi_hsync active pulse in a line. Can be configured in CONF state.
HSYNC_IDLE_POL

It is the idle value of spi_hsync. Can be configured in CONF state.
LCD_HSYNC_POSITION

It is the position of spi_hsync active pulse in a line. Can be configured in CONF state.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data